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Intel reveals new common CPU architecture


Intel CEO Paul Otellini announced today in his keynote address at the Intel Developer Forum that Intel will be moving its future CPUs to a common architecture. He said the architecture will incorporate the best of the current Netburst and mobile architectures, with a focus on delivering more performance per watt. The architecture will be used in mobile platforms (code-named Merom), desktops (Conroe), and servers (Woodcrest). This processor architecture will feature a range of next-generation Intel technologies, including 64-bit compatibility (EM64T), virtualization (VT), Intel's LaGrande security features, and Intel Active Management Tech (iAMT).

These CPUs are dual-core products built on Intel's 65nm process technology, and Otellini presented live demos of all three processors running various operating systems. Otellini's presentation was driven by a Merom-based laptop. He showed Linux running on the desktop-targeted Conroe chip and Windows Server 2003 on Woodcrest. Otellini said the silicon is already "running quite well," and the company expects to ship products in the second half of 2006.

Otellini said Conroe should deliver five times the performance per watt of the Netburst microarchitecture in desktop platforms.


At 14 stages, the main pipeline will be a little bit longer than current Pentium M processors. The cores will be a wider, more parallel design capable of issuing, executing, and retiring four instructions at once. (Current x86 processors are generally three-issue.) The CPU will, of course, feature out-of-order instruction execution and will also have deeper buffers than current Intel processors. These design changes should give the new architecture significantly more performance per clock, and somewhat consequently, higher performance per watt.

Unlike Intel's current dual-core CPU designs, which don't really share resources or communicate with one another except over the front-side bus, this new design looks to be a much more intentionally multicore design. The on-die L2 cache will be shared between the two cores, and Intel says the relative bandwidth per core will be higher than its current chips. L2 cache size is widely scalable to different sizes for different products. The L1 caches will remain separate and tied to a specific core, but the CPU will be able to transfer data directly from one core's L1 cache to another. Naturally, these CPUs will thus have two cores on a single die.

The first implementation of the architecture will not include Hyper-Threading, but Intel (somewhat cryptically) says to expect additional threads over time. I don't believe that means HT capability will be built into silicon but not initially made active, because Intel expressly cited transistor budget as a reason for excluding HT.
The real question is, how affordable will these be compared to AMD's X2 series. And will the cores be slow like the Pentium Ds?